1. Field of the Invention
The invention relates to a process for the deposition of a noble metal, barrier metal, or insulating layer in a trench or via in a semiconductor substrate to form a conformal electrode-metallization layer, barrier-metallization layer, or insulating layer.
2. Description of the Related Art
The reduction in memory cell size required for high density dynamic random access memories (DRAMs) results in a corresponding decrease in the area available for the storage node of the memory cell capacitor. Yet, design and operational parameters determine the minimum charge required for reliable operation of the memory cell despite decreasing cell area. Several techniques have been developed to increase the total charge capacity of the cell capacitor without significantly affecting the cell area. These include structures utilizing trench capacitors, as well as the utilization of new capacitor dielectric materials having higher dielectric constants.
U.S. Pat. No. 5,753,558 describes a typical prior art trench capacitor as shown in FIG. 1. It has a trench 4 in a silicon substrate 10 with a polysilicon bottom electrode 6, a dielectric layer 8, and a polysilicon top electrode 9 that fills in the trench.
With respect to dielectric materials there has been a major effort in semiconductor companies, worldwide, to commercialize high dielectric constant and ferroelectric thin films for capacitors in advanced DRAMs and ferroelectric random access memories (FeRAMs), respectively. These materials include BaSrTiO.sub.3 (BST) for DRAMs and PbZrTiO.sub.3 (PZT) and SrBi.sub.2 Ti.sub.2 O.sub.9 (SBT) for FeRAMs. Due to the highly oxidizing conditions encountered during deposition of the dielectric, it is well known that these materials require electrodes comprised of noble metals or noble metal alloys such as Pt, Ir, IrO.sub.2, Pt-Ru, etc. Still a further requirement is the sub-micron patterning of both the noble metals and the ferroelectric films.
Adverse interactions between the high dielectric constant material and both the substrate and metallization layer occur during device process steps including and following the deposition of the first metallization layer. A suitable barrier layer is employed to prevent unwanted reactions. A titanium nitride (TiN) barrier layer has been used between a platinum electrode and an aluminum metallization over SrBi.sub.2 Ta.sub.2 O.sub.9 (SBT). A titanium tungsten (TiW) barrier layer has been used between a platinum or titanium electrode and an aluminum metallization over PbZrTiO.sub.3 (PZT). In many cases a noble metal electrode and a barrier metal would be combined to form one composite metallization layer.
One of the critical considerations in depositing noble metal electrodes or barrier metallization layers is achieving a conformal film when depositing on non-planar structures such as trenches or vias. The problem is the geometric-shadowing and angle-of-incidence effects on coverage and microstructure. Thus when coating a step, deposition conditions that produce a dense structure on a flat surface yield a porous structure on the step side walls, and produce an open boundary or cusp emanating from the base of the step as a result of self-shadowing. "Semiconductor Materials and Process Technology Handbook" by Gary E. McGuire, Noyes Publications, 1988, PPS 440-443, hereby incorporated by reference, discloses details of step coverage and conventional solutions.
The techniques used to improve step coverage can be classified into the following broad categories: (1) source geometry adjustments, (2) step geometry shape adjustments, (3) substrate temperature control, and (4) bias sputtering.
Source geometry considerations are based on the fact that coating atoms approach a substrate surface in directions that are dependent on the geometric configuration of the deposition apparatus. Even in the case of sputtering at elevated pressures, the atoms approach the substrate line-of-sight from the point of last collision, which is nominally one mean free path from the substrate. A typical mean free path at 50 mTorr is of the order of 1 millimeter and therefore much larger than the step sizes.
The use of large source magnetron systems to deposit non-planar layers is advantageous for a number of reasons. In addition to providing improved source geometry adjustments to promote step coverage, they have the capacity for large production volumes and are compatible with in-line processing systems. In addition to magnetron sputtering sources, a wide range of sputter apparatus are available including ion beam and RF systems.
Step geometry shape control (i.e. tapered sidewalls in a step) is one of the most effective methods for reducing the geometric shadowing problems associated with step coverage. For example, a step slope of 30.degree. from the normal in combination with suitable substrate motion can eliminate cusp formation due to shadowing.
Increasing the substrate temperature increases the adatom surface diffusion and tends to negate the effects of self-shadowing.
The combination of source geometry adjustments, tapered steps, and substrate heating has proven adequate for providing acceptable aluminum metallization on most conventional devices. However, the use of tapered sidewalls is not compatible with the footprint requirements and shrinking lateral dimensions of ULSI.
For devices requiring sub-micron tolerances, bias sputtering is used to provide step coverage. In the bias sputtering method, improvements in surface coverage are achieved by re-sputtering material previously deposited. Thus some of the material deposited at the bottom of a step in a surface is resputtered at small angles and redeposited on the sidewalls of the step. The bias voltage and current must be selected to provide a proper balance between the deposition and resputtering processes. FIG. 2 shows the effect of bias voltage in contouring SiO.sub.2 films at a step. As the bias voltage increases the bias sputtering successfully eliminates crevice formation from the base of the step. Recent experiments have demonstrated that excellent step coverage of SiO.sub.2 over straight edge profiles can be obtained with a combination of rf sputtering from a planar magnetron source and an rf bias applied to the substrates. Furthermore, it has been shown that proper programming of the deposition and re-sputtering will permit surface insulator layers to be leveled in anticipation of subsequent layers of metallization. The use of bias sputtering eliminates porosity and improves the step coverage.